(1) Field of the Invention
This invention relates to the formation of high capacitance capacitors on integrated circuit wafers and more particularly to capacitor plates using etchback of polysilicon hemispherical grains.
(2) Description of the Related Art
Polysilicon hemispherical grains, HSG polysilicon, are used to increase surface area of capacitor plates used to form integrated circuit capacitors, particularly for DRAM circuits. The HSG polysilicon is formed on a conductor, usually polysilicon, used to form capacitor plates. Etchback of the HSG polysilicon using vertical anisotropic etching forms an irregular top surface of the capacitor plates. HSG polysilicon is also used on the sidewalls of the capacitor plates however adhesion of the HSG polysilicon to the sidewalls can be a problem.
U.S. Pat. No. 5,256,587 to Jun et al. describes methods of forming capacitor plates using a hemisphere particle layer having hills and valleys on a layer to be etched. The hemispherical particle layer is used on the top surface of the capacitor plates.
U.S. Pat. No. 5,254,503 to Kenny describes the use of sub-lithographic relief images to increase the surface area of the top surface of capacitor plates. Polysilicon and porous silicon can be used to form the sub-micron relief pattern.
U.S. Pat. No. 5,082,797 to Chan et al. describes the use of a texturized polysilicon structure to increase the area of capacitor plates. A polysilicon structure is subjected to a wet oxidation followed by a wet oxide etch to form the texturized polysilicon structure.
U.S. Pat. No. 5,447,878 to Park et al. describes the use of an HSG polysilicon layer of form extended surface area on both the top and the sidewalls of capacitor plates, however an anneal step after the formation of the HSG polysilicon layer and an timed oxide back etch is not described.
U.S. Pat. No. 5,492,848 to Lur et al. describes the use of silicon nodules formed on the top surface of capacitor plates to increase surface area.
U.S. Pat. No. 5,134,086 to Ahn describes exposing a first polysilicon layer, an oxide layer, and a second polysilicon layer consisting of grains to an oxide etchant. The oxide etchant penetrates the grain boundaries of the second polysilicon layer and etches the oxide layer at the grain boundaries. The etching forms an irregular surface which increases surface area. The irregular surface area is on the top surface of the capacitor plates.
U.S. Pat. No. 5,358,888 to Ahn et al. describes the use of polysilicon hemispherical grains to form an irregular surface on the top surface of capacitor plates.
A paper entitled "A CAPACITOR-OVER-BIT-LINE (COB) CELL WITH A HEMISPHERICAL-GRAIN STORAGE NODE FOR 64 Mb DRAMs", by Sakao et al., IEDM, 1990, pages 27.3.1-27.3.4 describes using etchback of HSG polysilicon to increase the surface area of capacitor plates. The use of an anneal step or a timed oxide etchback step is not described.
This invention describes the use of HSG polysilicon along with an anneal step and a timed oxide etchback step to form an irregular surface on the top and sidewalls of capacitor plates thereby increasing surface area and capacitance. The method of this invention prevents individual grains from breaking away thereby resulting in improved chip yield.